diff --git a/libs/libmraa/Makefile b/libs/libmraa/Makefile new file mode 100644 index 000000000..3e3202ad2 --- /dev/null +++ b/libs/libmraa/Makefile @@ -0,0 +1,51 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_NAME:=libmraa +PKG_VERSION:=0.8.0 + +PKG_RELEASE=$(PKG_SOURCE_VERSION) + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://github.com/intel-iot-devkit/mraa.git +PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION) +PKG_SOURCE_VERSION:=70600dece4138b0c0dbaff42f57828f1559cd840 +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.gz +PKG_BUILD_DEPENDS:=node python/host swig/host node/host +CMAKE_INSTALL:=1 + +PKG_MAINTAINER:=John Crispin +PKG_LICENSE:=LGPL-2.1 + +include $(INCLUDE_DIR)/package.mk +include $(INCLUDE_DIR)/cmake.mk + +CMAKE_OPTIONS=-DBUILDARCH=$(CONFIG_ARCH) \ + -DENABLEEXAMPLES=0 \ + -DNODE_EXECUTABLE=$(STAGING_DIR_HOST)/bin/node \ + -DSWIG_DIR=$(STAGING_DIR_HOST)/bin + +TARGET_CFLAGS+=-I$(STAGING_DIR)/usr/include/node + +define Package/libmraa + SECTION:=libs + CATEGORY:=Libraries + DEPENDS:=+python +libstdcpp + TITLE:=Intel IoT lowlevel IO library +endef + +define Package/libmraa/install + $(INSTALL_DIR) $(1)/usr/lib/{node/mraa,python2.7/site-packages} $(1)/usr/bin + $(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/lib/libmraa.so* $(1)/usr/lib/ + $(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/lib/node_modules/mraa/* $(1)/usr/lib/node/mraa/ + $(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/lib/python2.7/site-packages/* $(1)/usr/lib/python2.7/site-packages/ +# $(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/share/mraa/examples/python/blink-io8.py $(1)/usr/bin/ +endef + +$(eval $(call BuildPackage,libmraa)) diff --git a/libs/libmraa/patches/0001-base.patch b/libs/libmraa/patches/0001-base.patch new file mode 100644 index 000000000..5094389f4 --- /dev/null +++ b/libs/libmraa/patches/0001-base.patch @@ -0,0 +1,118 @@ +From 6fecad819376442d057bdd35a0909cfac9df02f5 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 23 Jul 2015 12:18:39 +0200 +Subject: [PATCH 1/4] base + +--- + CMakeLists.txt | 10 ++++------ + api/mraa/types.h | 1 + + include/mraa_internal.h | 7 +++++++ + src/CMakeLists.txt | 5 +++++ + src/i2c/i2c.c | 2 +- + src/mraa.c | 3 +++ + src/uart/uart.c | 1 + + 7 files changed, 22 insertions(+), 7 deletions(-) + +--- a/CMakeLists.txt ++++ b/CMakeLists.txt +@@ -14,12 +14,7 @@ + set (CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake/modules ${CMAKE_MODULE_PATH}) + + # Make a version file containing the current version from git. +-include (GetGitRevisionDescription) +-git_describe (VERSION "--tags") +-if ("x_${VERSION}" STREQUAL "x_GIT-NOTFOUND" OR "x_${VERSION}" STREQUAL "x_HEAD-HASH-NOTFOUND") +- message (WARNING " - Install git to compile a production libmraa!") +- set (VERSION "v0.8.0-dirty") +-endif () ++set (VERSION "v0.8.0") + + message (INFO " - libmraa Version ${VERSION}") + +@@ -84,8 +79,10 @@ + set (X86PLAT ON) + elseif (DETECTED_ARCH MATCHES "arm.*") + set (ARMPLAT ON) ++elseif (DETECTED_ARCH MATCHES "mips") ++ set (MIPSPLAT ON) + else () +- message(FATAL_ERROR "Only x86 and arm platforms currently supported") ++ message(FATAL_ERROR "Only x86, arm and mips platforms currently supported") + endif() + + if (BUILDSWIGPYTHON) +--- a/api/mraa/types.h ++++ b/api/mraa/types.h +@@ -46,6 +46,7 @@ + MRAA_BEAGLEBONE = 6, /**< The different BeagleBone Black Modes B/C */ + MRAA_BANANA = 7, /**< Allwinner A20 based Banana Pi and Banana Pro */ + MRAA_INTEL_NUC5 = 8, /**< The Intel 5th generations Broadwell NUCs */ ++ MRAA_MTK_LINKIT = 9, /**< Mediatek MT7688 based Linkit (Air) */ + + // USB platform extenders start at 256 + MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */ +--- a/include/mraa_internal.h ++++ b/include/mraa_internal.h +@@ -66,6 +66,13 @@ + mraa_platform_t mraa_usb_platform_extender(mraa_board_t* board); + + /** ++ * runtime detect running arm platforms ++ * ++ * @return mraa_platform_t of the init'ed platform ++ */ ++mraa_platform_t mraa_mips_platform(); ++ ++/** + * helper function to check if file exists + * + * @param filename to check +--- a/src/CMakeLists.txt ++++ b/src/CMakeLists.txt +@@ -71,6 +71,11 @@ + add_subdirectory(usb) + endif () + ++if (MIPSPLAT) ++ add_subdirectory(mips) ++ set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMIPSPLAT=1") ++endif() ++ + set (mraa_LIB_SRCS + ${mraa_LIB_PLAT_SRCS_NOAUTO} + # autogenerated version file +--- a/src/i2c/i2c.c ++++ b/src/i2c/i2c.c +@@ -31,9 +31,9 @@ + #include + #include + #include ++#include + #include + #include +-#include + #include + #include "linux/i2c-dev.h" + +--- a/src/mraa.c ++++ b/src/mraa.c +@@ -111,6 +111,9 @@ + #elif defined(ARMPLAT) + // Use runtime ARM platform detection + platform_type = mraa_arm_platform(); ++#elif MIPSPLAT ++ // Use runtime ARM platform detection ++ platform_type = mraa_mips_platform(); + #else + #error mraa_ARCH NOTHING + #endif +--- a/src/uart/uart.c ++++ b/src/uart/uart.c +@@ -26,6 +26,7 @@ + + #include + #include ++#include + #include + #include + #include diff --git a/libs/libmraa/patches/0002-add-mips-support.patch b/libs/libmraa/patches/0002-add-mips-support.patch new file mode 100644 index 000000000..66219b9fe --- /dev/null +++ b/libs/libmraa/patches/0002-add-mips-support.patch @@ -0,0 +1,483 @@ +From 2c67c6f51ce5bab18c79f4304ccf42716f59f13c Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 23 Jul 2015 13:21:25 +0200 +Subject: [PATCH 2/4] add mips support + +Signed-off-by: John Crispin +--- + include/mips/mediatek.h | 39 ++++++ + src/mips/CMakeLists.txt | 6 + + src/mips/mediatek.c | 349 +++++++++++++++++++++++++++++++++++++++++++++++ + src/mips/mips.c | 60 ++++++++ + 4 files changed, 454 insertions(+) + create mode 100644 include/mips/mediatek.h + create mode 100644 src/mips/CMakeLists.txt + create mode 100644 src/mips/mediatek.c + create mode 100644 src/mips/mips.c + +--- /dev/null ++++ b/include/mips/mediatek.h +@@ -0,0 +1,39 @@ ++/* ++ * Author: Thomas Ingleby ++ * Author: Michael Ring ++ * Copyright (c) 2014 Intel Corporation. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining ++ * a copy of this software and associated documentation files (the ++ * "Software"), to deal in the Software without restriction, including ++ * without limitation the rights to use, copy, modify, merge, publish, ++ * distribute, sublicense, and/or sell copies of the Software, and to ++ * permit persons to whom the Software is furnished to do so, subject to ++ * the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE ++ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION ++ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION ++ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#pragma once ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "mraa_internal.h" ++ ++mraa_board_t * ++ mraa_mtk_linkit(); ++ ++#ifdef __cplusplus ++} ++#endif +--- /dev/null ++++ b/src/mips/CMakeLists.txt +@@ -0,0 +1,6 @@ ++message (INFO " - Adding MIPS platforms") ++set (mraa_LIB_PLAT_SRCS_NOAUTO ${mraa_LIB_SRCS_NOAUTO} ++ ${PROJECT_SOURCE_DIR}/src/mips/mips.c ++ ${PROJECT_SOURCE_DIR}/src/mips/mediatek.c ++ PARENT_SCOPE ++) +--- /dev/null ++++ b/src/mips/mediatek.c +@@ -0,0 +1,349 @@ ++/* ++ * Author: Thomas Ingleby ++ * Author: Michael Ring ++ * Copyright (c) 2014 Intel Corporation. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining ++ * a copy of this software and associated documentation files (the ++ * "Software"), to deal in the Software without restriction, including ++ * without limitation the rights to use, copy, modify, merge, publish, ++ * distribute, sublicense, and/or sell copies of the Software, and to ++ * permit persons to whom the Software is furnished to do so, subject to ++ * the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE ++ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION ++ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION ++ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mraa_internal.h" ++ ++#include "common.h" ++ ++#define PLATFORM_MEDIATEK_LINKIT 1 ++#define PLATFORM_MEDIATEK_LINKIT_AIR 2 ++#define MMAP_PATH "/dev/mem" ++#define MT7628_GPIO_BASE 0x100 ++#define MT7628_BLOCK_SIZE (4 * 1024) ++#define MT7628_GPIO_CTRL 0x00 ++#define MT7628_GPIO_DATA 0x20 ++#define MT7628_GPIO_SET 0x30 ++#define MT7628_GPIO_CLEAR 0x40 ++ ++#define MAX_SIZE 64 ++ ++// MMAP ++static uint8_t* mmap_reg = NULL; ++static int mmap_fd = 0; ++static int mmap_size; ++static unsigned int mmap_count = 0; ++static int platform_detected = 0; ++ ++mraa_result_t ++mraa_mtk_linkit_mmap_write(mraa_gpio_context dev, int value) ++{ ++ volatile uint32_t* addr; ++ if (value) { ++ *(volatile uint32_t*) (mmap_reg + MT7628_GPIO_SET + (dev->pin / 32) * 4) = ++ (uint32_t)(1 << (dev->pin % 32)); ++ } else { ++ *(volatile uint32_t*) (mmap_reg + MT7628_GPIO_CLEAR + (dev->pin / 32) * 4) = ++ (uint32_t)(1 << (dev->pin % 32)); ++ } ++ return MRAA_SUCCESS; ++} ++ ++static mraa_result_t ++mraa_mtk_linkit_mmap_unsetup() ++{ ++ if (mmap_reg == NULL) { ++ syslog(LOG_ERR, "linkit mmap: null register cant unsetup"); ++ return MRAA_ERROR_INVALID_RESOURCE; ++ } ++ munmap(mmap_reg, mmap_size); ++ mmap_reg = NULL; ++ if (close(mmap_fd) != 0) { ++ return MRAA_ERROR_INVALID_RESOURCE; ++ } ++ return MRAA_SUCCESS; ++} ++ ++int ++mraa_mtk_linkit_mmap_read(mraa_gpio_context dev) ++{ ++ uint32_t value = *(volatile uint32_t*) (mmap_reg + MT7628_GPIO_DATA + (dev->pin / 32) * 4); ++ if (value & (uint32_t)(1 << (dev->pin % 32))) { ++ return 1; ++ } ++ return 0; ++} ++ ++mraa_result_t ++mraa_mtk_linkit_mmap_setup(mraa_gpio_context dev, mraa_boolean_t en) ++{ ++ if (dev == NULL) { ++ syslog(LOG_ERR, "linkit mmap: context not valid"); ++ return MRAA_ERROR_INVALID_HANDLE; ++ } ++ ++ if (en == 0) { ++ if (dev->mmap_write == NULL && dev->mmap_read == NULL) { ++ syslog(LOG_ERR, "linkit mmap: can't disable disabled mmap gpio"); ++ return MRAA_ERROR_INVALID_PARAMETER; ++ } ++ dev->mmap_write = NULL; ++ dev->mmap_read = NULL; ++ mmap_count--; ++ if (mmap_count == 0) { ++ return mraa_mtk_linkit_mmap_unsetup(); ++ } ++ return MRAA_SUCCESS; ++ } ++ ++ if (dev->mmap_write != NULL && dev->mmap_read != NULL) { ++ syslog(LOG_ERR, "linkit mmap: can't enable enabled mmap gpio"); ++ return MRAA_ERROR_INVALID_PARAMETER; ++ } ++ ++ // Might need to make some elements of this thread safe. ++ // For example only allow one thread to enter the following block ++ // to prevent mmap'ing twice. ++ if (mmap_reg == NULL) { ++ if ((mmap_fd = open(MMAP_PATH, O_RDWR)) < 0) { ++ syslog(LOG_ERR, "linkit map: unable to open resource0 file"); ++ return MRAA_ERROR_INVALID_HANDLE; ++ } ++ ++ mmap_reg = (uint8_t*) mmap(NULL, MT7628_BLOCK_SIZE, PROT_READ | PROT_WRITE, ++ MAP_FILE | MAP_SHARED, mmap_fd, MT7628_GPIO_BASE); ++ if (mmap_reg == MAP_FAILED) { ++ syslog(LOG_ERR, "linkit mmap: failed to mmap"); ++ mmap_reg = NULL; ++ close(mmap_fd); ++ return MRAA_ERROR_NO_RESOURCES; ++ } ++ } ++ dev->mmap_write = &mraa_mtk_linkit_mmap_write; ++ dev->mmap_read = &mraa_mtk_linkit_mmap_read; ++ mmap_count++; ++ ++ return MRAA_SUCCESS; ++} ++ ++mraa_board_t* ++mraa_mtk_linkit() ++{ ++ mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t)); ++ if (b == NULL) { ++ return NULL; ++ } ++ ++ b->platform_name = "LINKIT"; ++ platform_detected = PLATFORM_MEDIATEK_LINKIT; ++ b->phy_pin_count = 31; ++ ++ b->aio_count = 0; ++ b->adc_raw = 0; ++ b->adc_supported = 0; ++ b->pwm_default_period = 500; ++ b->pwm_max_period = 2147483; ++ b->pwm_min_period = 1; ++ ++ b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * b->phy_pin_count); ++ ++ advance_func->gpio_mmap_setup = &mraa_mtk_linkit_mmap_setup; ++ ++ strncpy(b->pins[0].name, "P0", MRAA_PIN_NAME_SIZE); ++ b->pins[0].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; ++ ++ strncpy(b->pins[1].name, "P1", MRAA_PIN_NAME_SIZE); ++ b->pins[1].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; ++ ++ strncpy(b->pins[2].name, "P2", MRAA_PIN_NAME_SIZE); ++ b->pins[2].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; ++ ++ strncpy(b->pins[3].name, "P3", MRAA_PIN_NAME_SIZE); ++ b->pins[3].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; ++ ++ strncpy(b->pins[4].name, "P4", MRAA_PIN_NAME_SIZE); ++ b->pins[4].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; ++ ++ strncpy(b->pins[5].name, "P5", MRAA_PIN_NAME_SIZE); ++ b->pins[5].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; ++ ++ strncpy(b->pins[6].name, "P6", MRAA_PIN_NAME_SIZE); ++ b->pins[6].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; ++ ++ strncpy(b->pins[7].name, "P7", MRAA_PIN_NAME_SIZE); ++ b->pins[7].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; ++ ++ strncpy(b->pins[8].name, "P8", MRAA_PIN_NAME_SIZE); ++ b->pins[8].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; ++ b->pins[8].gpio.pinmap = 21; ++ b->pins[8].uart.parent_id = 2; ++ b->pins[8].uart.mux_total = 0; ++ ++ strncpy(b->pins[9].name, "P9", MRAA_PIN_NAME_SIZE); ++ b->pins[9].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; ++ b->pins[9].gpio.pinmap = 20; ++ b->pins[9].uart.parent_id = 2; ++ b->pins[9].uart.mux_total = 0; ++ ++ strncpy(b->pins[10].name, "P10", MRAA_PIN_NAME_SIZE); ++ b->pins[10].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[10].gpio.pinmap = 2; ++ ++ strncpy(b->pins[11].name, "P11", MRAA_PIN_NAME_SIZE); ++ b->pins[11].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[11].gpio.pinmap = 3; ++ ++ strncpy(b->pins[12].name, "P12", MRAA_PIN_NAME_SIZE); ++ b->pins[12].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[12].gpio.pinmap = 0; ++ ++ strncpy(b->pins[13].name, "P13", MRAA_PIN_NAME_SIZE); ++ b->pins[13].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[13].gpio.pinmap = 1; ++ ++ strncpy(b->pins[14].name, "P14", MRAA_PIN_NAME_SIZE); ++ b->pins[14].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; ++ ++ strncpy(b->pins[15].name, "P15", MRAA_PIN_NAME_SIZE); ++ b->pins[15].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[15].gpio.pinmap = 44; ++ ++ strncpy(b->pins[16].name, "P16", MRAA_PIN_NAME_SIZE); ++ b->pins[16].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; ++ b->pins[16].gpio.pinmap = 46; ++ b->pins[16].uart.parent_id = 1; ++ b->pins[16].uart.mux_total = 0; ++ ++ strncpy(b->pins[17].name, "P17", MRAA_PIN_NAME_SIZE); ++ b->pins[17].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; ++ b->pins[17].gpio.pinmap = 45; ++ b->pins[17].uart.parent_id = 1; ++ b->pins[17].uart.mux_total = 0; ++ ++ strncpy(b->pins[18].name, "P18", MRAA_PIN_NAME_SIZE); ++ b->pins[18].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; ++ b->pins[18].gpio.pinmap = 13; ++ b->pins[18].uart.parent_id = 1; ++ b->pins[18].uart.mux_total = 0; ++ ++ strncpy(b->pins[19].name, "P19", MRAA_PIN_NAME_SIZE); ++ b->pins[19].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; ++ b->pins[19].gpio.pinmap = 12; ++ b->pins[19].uart.parent_id = 0; ++ b->pins[19].uart.mux_total = 0; ++ ++ strncpy(b->pins[20].name, "P20", MRAA_PIN_NAME_SIZE); ++ b->pins[20].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 1, 0, 0 }; ++ b->pins[20].gpio.pinmap = 5; ++ b->pins[20].i2c.pinmap = 0; ++ b->pins[20].i2c.mux_total = 0; ++ ++ strncpy(b->pins[21].name, "P21", MRAA_PIN_NAME_SIZE); ++ b->pins[21].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 1, 0, 0 }; ++ b->pins[21].gpio.pinmap = 4; ++ b->pins[21].i2c.pinmap = 0; ++ b->pins[21].i2c.mux_total = 0; ++ ++ strncpy(b->pins[22].name, "P22", MRAA_PIN_NAME_SIZE); ++ b->pins[22].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 1, 0, 0, 0 }; ++ b->pins[22].gpio.pinmap = 8; ++ b->pins[22].spi.pinmap = 0; ++ b->pins[22].spi.mux_total = 0; ++ ++ strncpy(b->pins[23].name, "P23", MRAA_PIN_NAME_SIZE); ++ b->pins[23].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 1, 0, 0, 0 }; ++ b->pins[23].gpio.pinmap = 9; ++ b->pins[23].spi.pinmap = 0; ++ b->pins[23].spi.mux_total = 0; ++ ++ strncpy(b->pins[24].name, "P24", MRAA_PIN_NAME_SIZE); ++ b->pins[24].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 1, 0, 0, 0 }; ++ b->pins[24].gpio.pinmap = 7; ++ b->pins[24].spi.pinmap = 0; ++ b->pins[24].spi.mux_total = 0; ++ ++ strncpy(b->pins[25].name, "P25", MRAA_PIN_NAME_SIZE); ++ b->pins[25].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 1, 0, 0, 0 }; ++ b->pins[25].gpio.pinmap = 6; ++ b->pins[25].spi.pinmap = 0; ++ b->pins[25].spi.mux_total = 0; ++ ++ strncpy(b->pins[26].name, "P26", MRAA_PIN_NAME_SIZE); ++ b->pins[26].capabilites = (mraa_pincapabilities_t){ 1, 1, 1, 0, 0, 0, 0, 0 }; ++ b->pins[26].gpio.pinmap = 18; ++ ++ strncpy(b->pins[27].name, "P27", MRAA_PIN_NAME_SIZE); ++ b->pins[27].capabilites = (mraa_pincapabilities_t){ 1, 1, 1, 0, 0, 0, 0, 0 }; ++ b->pins[27].gpio.pinmap = 19; ++ ++ strncpy(b->pins[28].name, "P28", MRAA_PIN_NAME_SIZE); ++ b->pins[28].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[28].gpio.pinmap = 16; ++ ++ strncpy(b->pins[29].name, "P29", MRAA_PIN_NAME_SIZE); ++ b->pins[29].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[29].gpio.pinmap = 17; ++ ++ strncpy(b->pins[30].name, "P30", MRAA_PIN_NAME_SIZE); ++ b->pins[30].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[30].gpio.pinmap = 14; ++ ++ strncpy(b->pins[31].name, "P31", MRAA_PIN_NAME_SIZE); ++ b->pins[31].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[31].gpio.pinmap = 15; ++ ++ // BUS DEFINITIONS ++ b->i2c_bus_count = 1; ++ b->def_i2c_bus = 0; ++ b->i2c_bus[0].bus_id = 0; ++ b->i2c_bus[0].sda = 20; ++ b->i2c_bus[0].scl = 21; ++ ++ b->spi_bus_count = 1; ++ b->def_spi_bus = 0; ++ b->spi_bus[0].bus_id = 0; ++ b->spi_bus[0].slave_s = 0; ++ b->spi_bus[0].cs = 25; ++ b->spi_bus[0].mosi = 22; ++ b->spi_bus[0].miso = 23; ++ b->spi_bus[0].sclk = 21; ++ ++ b->uart_dev_count = 3; ++ b->def_uart_dev = 0; ++ b->uart_dev[0].rx = 18; ++ b->uart_dev[0].tx = 19; ++ ++ b->uart_dev[1].rx = 16; ++ b->uart_dev[1].tx = 17; ++ ++ b->uart_dev[2].rx = 9; ++ b->uart_dev[2].tx = 8; ++ ++ b->gpio_count = 0; ++ int i; ++ for (i = 0; i < b->phy_pin_count; i++) { ++ if (b->pins[i].capabilites.gpio) { ++ b->gpio_count++; ++ } ++ } ++ ++ return b; ++} +--- /dev/null ++++ b/src/mips/mips.c +@@ -0,0 +1,60 @@ ++/* ++ * Author: Thomas Ingleby ++ * Author: Michael Ring ++ * Copyright (c) 2014 Intel Corporation. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining ++ * a copy of this software and associated documentation files (the ++ * "Software"), to deal in the Software without restriction, including ++ * without limitation the rights to use, copy, modify, merge, publish, ++ * distribute, sublicense, and/or sell copies of the Software, and to ++ * permit persons to whom the Software is furnished to do so, subject to ++ * the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE ++ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION ++ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION ++ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include ++#include ++ ++#include "mraa_internal.h" ++#include "mips/mediatek.h" ++ ++mraa_platform_t ++mraa_mips_platform() ++{ ++ mraa_platform_t platform_type = MRAA_UNKNOWN_PLATFORM; ++ size_t len = 100; ++ char* line = malloc(len); ++ FILE* fh = fopen("/proc/cpuinfo", "r"); ++ if (fh != NULL) { ++ while (getline(&line, &len, fh) != -1) { ++ if (strncmp(line, "machine", 7) == 0) { ++ if (strstr(line, "MediaTek LinkIt Smart7688")) { ++ platform_type = MRAA_MTK_LINKIT; ++ } ++ } ++ } ++ fclose(fh); ++ } ++ free(line); ++ ++ switch (platform_type) { ++ case MRAA_MTK_LINKIT: ++ plat = mraa_mtk_linkit(); ++ break; ++ default: ++ plat = NULL; ++ syslog(LOG_ERR, "Unknown Platform, currently not supported by MRAA"); ++ } ++ return platform_type; ++} diff --git a/libs/libmraa/patches/0003-uart.patch b/libs/libmraa/patches/0003-uart.patch new file mode 100644 index 000000000..647abc5f2 --- /dev/null +++ b/libs/libmraa/patches/0003-uart.patch @@ -0,0 +1,26 @@ +From 9540f9b93704e8e80ab2048954ca88d8e6eddf86 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 23 Jul 2015 16:43:42 +0200 +Subject: [PATCH 3/4] uart + +--- + src/uart/uart.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/src/uart/uart.c b/src/uart/uart.c +index 3ef55a4..5102f81 100644 +--- a/src/uart/uart.c ++++ b/src/uart/uart.c +@@ -34,6 +34,9 @@ + #include "uart.h" + #include "mraa_internal.h" + ++#ifndef CMSPAR ++#define CMSPAR 010000000000 ++#endif + // This function takes an unsigned int and converts it to a B* speed_t + // that can be used with linux/posix termios + static speed_t +-- +1.7.10.4 + diff --git a/libs/libmraa/patches/0004-fixes.patch b/libs/libmraa/patches/0004-fixes.patch new file mode 100644 index 000000000..40e5930ee --- /dev/null +++ b/libs/libmraa/patches/0004-fixes.patch @@ -0,0 +1,666 @@ +From 3c34e5f87a741ec2fc7809fc8c169a832275d32c Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 23 Jul 2015 18:19:32 +0200 +Subject: [PATCH 4/4] fixes + +--- + src/mips/mediatek.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/src/mips/mediatek.c ++++ b/src/mips/mediatek.c +@@ -37,12 +37,12 @@ + #define PLATFORM_MEDIATEK_LINKIT 1 + #define PLATFORM_MEDIATEK_LINKIT_AIR 2 + #define MMAP_PATH "/dev/mem" +-#define MT7628_GPIO_BASE 0x100 +-#define MT7628_BLOCK_SIZE (4 * 1024) +-#define MT7628_GPIO_CTRL 0x00 +-#define MT7628_GPIO_DATA 0x20 +-#define MT7628_GPIO_SET 0x30 +-#define MT7628_GPIO_CLEAR 0x40 ++#define MT7628_GPIOMODE_BASE 0x10000000 ++#define MT7628_BLOCK_SIZE 0x1000 ++#define MT7628_GPIO_CTRL 0x600 ++#define MT7628_GPIO_DATA 0x620 ++#define MT7628_GPIO_SET 0x630 ++#define MT7628_GPIO_CLEAR 0x640 + + #define MAX_SIZE 64 + +@@ -50,6 +50,9 @@ + static uint8_t* mmap_reg = NULL; + static int mmap_fd = 0; + static int mmap_size; ++static uint8_t* gpio_mmap_reg = NULL; ++static int gpio_mmap_fd = 0; ++static int gpio_mmap_size; + static unsigned int mmap_count = 0; + static int platform_detected = 0; + +@@ -129,9 +132,10 @@ + } + + mmap_reg = (uint8_t*) mmap(NULL, MT7628_BLOCK_SIZE, PROT_READ | PROT_WRITE, +- MAP_FILE | MAP_SHARED, mmap_fd, MT7628_GPIO_BASE); ++ MAP_FILE | MAP_SHARED, mmap_fd, 0x10000000); + if (mmap_reg == MAP_FAILED) { +- syslog(LOG_ERR, "linkit mmap: failed to mmap"); ++ perror("foo"); ++ syslog(LOG_ERR, "linkit mmap: failed to mmap"); + mmap_reg = NULL; + close(mmap_fd); + return MRAA_ERROR_NO_RESOURCES; +@@ -144,201 +148,442 @@ + return MRAA_SUCCESS; + } + ++static int mmap_gpiomode(void) ++{ ++ if ((gpio_mmap_fd = open(MMAP_PATH, O_RDWR)) < 0) { ++ syslog(LOG_ERR, "linkit map: unable to open resource0 file"); ++ return MRAA_ERROR_INVALID_HANDLE; ++ } ++ ++ gpio_mmap_reg = (uint8_t*) mmap(NULL, MT7628_BLOCK_SIZE, PROT_READ | PROT_WRITE, ++ MAP_FILE | MAP_SHARED, gpio_mmap_fd, MT7628_GPIOMODE_BASE); ++ if (gpio_mmap_reg == MAP_FAILED) { ++ syslog(LOG_ERR, "linkit gpio_mmap: failed to mmap"); ++ gpio_mmap_reg = NULL; ++ close(gpio_mmap_fd); ++ return MRAA_ERROR_NO_RESOURCES; ++ } ++ return 0; ++} ++ ++static void set_gpiomode(unsigned int mask, unsigned int shift, unsigned int val) ++{ ++ unsigned int reg; ++ unsigned int offset = 0x60; ++ ++ if (shift >= 32) { ++ shift -= 32; ++ offset += 4; ++ } ++ ++ reg = *(volatile uint32_t*) (gpio_mmap_reg + offset); ++ ++ reg &= ~(mask << shift); ++ reg |= (val << shift); ++ *(volatile uint32_t*) (gpio_mmap_reg + offset) = reg; ++} ++ ++enum { ++ MUX_GPIO = 0, ++ MUX_SPI_S, ++ MUX_SPI_CS1, ++ MUX_I2S, ++ MUX_UART0, ++ MUX_I2C, ++ MUX_UART1, ++ MUX_UART2, ++ MUX_PWM0, ++ MUX_PWM1, ++ MUX_EPHY, ++ MUX_WLED, ++ __MUX_MAX, ++}; ++ ++static unsigned char gpio_mux_groups[64]; ++static struct pinmux { ++ char *name; ++ char *func[4]; ++ unsigned int shift; ++ unsigned int mask; ++} mt7688_mux[] = { ++ { ++ .name = "refclk", ++ .func = { "refclk", "gpio", NULL, NULL }, ++ .shift = 18, ++ .mask = 0x1, ++ }, { ++ .name = "spi_s", ++ .func = { "spi_s", "gpio", "utif", "pwm" }, ++ .shift = 2, ++ .mask = 0x3, ++ }, { ++ .name = "spi_cs1", ++ .func = { "spi_cs1", "gpio", NULL, "refclk" }, ++ .shift = 4, ++ .mask = 0x3, ++ }, { ++ .name = "i2s", ++ .func = { "i2s", "gpio", "pcm", NULL }, ++ .shift = 6, ++ .mask = 0x3, ++ }, { ++ .name = "uart0", ++ .func = { "uart", "gpio", NULL, NULL }, ++ .shift = 8, ++ .mask = 0x3, ++ }, { ++ .name = "i2c", ++ .func = { "i2c", "gpio", NULL, NULL }, ++ .shift = 20, ++ .mask = 0x3, ++ }, { ++ .name = "uart1", ++ .func = { "uart", "gpio", NULL, NULL }, ++ .shift = 24, ++ .mask = 0x3, ++ }, { ++ .name = "uart2", ++ .func = { "uart", "gpio", "pwm", NULL }, ++ .shift = 26, ++ .mask = 0x3, ++ }, { ++ .name = "pwm0", ++ .func = { "pwm", "gpio", NULL, NULL }, ++ .shift = 28, ++ .mask = 0x3, ++ }, { ++ .name = "pwm1", ++ .func = { "pwm", "gpio", NULL, NULL }, ++ .shift = 30, ++ .mask = 0x3, ++ }, { ++ .name = "ephy", ++ .func = { "ephy", "gpio", NULL, NULL }, ++ .shift = 34, ++ .mask = 0x3, ++ }, { ++ .name = "wled", ++ .func = { "wled", "gpio", NULL, NULL }, ++ .shift = 32, ++ .mask = 0x3, ++ }, ++}; ++ ++mraa_result_t gpio_init_pre(int pin) ++{ ++ struct pinmux *m = &mt7688_mux[gpio_mux_groups[pin]]; ++ ++ set_gpiomode(m->mask, m->shift, 1); ++ ++ return 0; ++} ++ ++static void gpiomode_set(unsigned int id, char *name) ++{ ++ int i; ++ ++ if (id >= __MUX_MAX) ++ return; ++ ++ for (i = 0; i < 4; i++) { ++ if (!mt7688_mux[id].func[i] || strcmp(mt7688_mux[id].func[i], name)) ++ continue; ++ set_gpiomode(mt7688_mux[id].mask, mt7688_mux[id].shift, i); ++ syslog(0, "mraa: set pinmux %s -> %s\n", mt7688_mux[id].name, name); ++ return; ++ } ++} ++ ++mraa_result_t i2c_init_pre(unsigned int bus) ++{ ++ gpiomode_set(MUX_I2C, "i2c"); ++ return 0; ++} ++ ++mraa_result_t ++pwm_init_post(mraa_pwm_context pwm) ++{ ++ switch(pwm->pin) { ++ case 0: ++ gpiomode_set(MUX_PWM0, "pwm"); ++ break; ++ case 1: ++ gpiomode_set(MUX_PWM1, "pwm"); ++ break; ++ case 2: ++ case 3: ++ gpiomode_set(MUX_UART2, "pwm"); ++ break; ++ } ++ return 0; ++} ++ ++mraa_result_t spi_init_pre(int bus) ++{ ++ gpiomode_set(MUX_SPI_CS1, "spi_cs1"); ++ return 0; ++} ++ ++mraa_result_t uart_init_pre(int index) ++{ ++ switch(index) { ++ case 0: ++ gpiomode_set(MUX_UART0, "uart"); ++ break; ++ case 1: ++ gpiomode_set(MUX_UART1, "uart"); ++ break; ++ case 2: ++ gpiomode_set(MUX_UART2, "uart"); ++ break; ++ } ++ return 0; ++} ++ ++mraa_result_t ++i2c_freq(mraa_i2c_context dev, mraa_i2c_mode_t mode) ++{ ++ switch (mode) { ++ case MRAA_I2C_STD: ++ break; ++ default: ++ syslog(LOG_ERR, "Invalid i2c frequency"); ++ break; ++ } ++ return MRAA_SUCCESS; ++} ++ ++ + mraa_board_t* + mraa_mtk_linkit() + { ++ int i; ++ ++ if (mmap_gpiomode()) ++ return NULL; ++ + mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t)); + if (b == NULL) { + return NULL; + } + +- b->platform_name = "LINKIT"; ++ memset(b, 0, sizeof(mraa_board_t)); ++ ++ b->platform_name = "LinkIt Smart 7688"; + platform_detected = PLATFORM_MEDIATEK_LINKIT; +- b->phy_pin_count = 31; ++ b->phy_pin_count = 64; + + b->aio_count = 0; + b->adc_raw = 0; + b->adc_supported = 0; + b->pwm_default_period = 500; +- b->pwm_max_period = 2147483; ++ b->pwm_max_period = 1000000; + b->pwm_min_period = 1; + +- b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * b->phy_pin_count); +- +- advance_func->gpio_mmap_setup = &mraa_mtk_linkit_mmap_setup; +- +- strncpy(b->pins[0].name, "P0", MRAA_PIN_NAME_SIZE); +- b->pins[0].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; +- +- strncpy(b->pins[1].name, "P1", MRAA_PIN_NAME_SIZE); +- b->pins[1].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; +- +- strncpy(b->pins[2].name, "P2", MRAA_PIN_NAME_SIZE); +- b->pins[2].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; +- +- strncpy(b->pins[3].name, "P3", MRAA_PIN_NAME_SIZE); +- b->pins[3].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; +- +- strncpy(b->pins[4].name, "P4", MRAA_PIN_NAME_SIZE); +- b->pins[4].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; +- +- strncpy(b->pins[5].name, "P5", MRAA_PIN_NAME_SIZE); +- b->pins[5].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; +- +- strncpy(b->pins[6].name, "P6", MRAA_PIN_NAME_SIZE); +- b->pins[6].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; +- +- strncpy(b->pins[7].name, "P7", MRAA_PIN_NAME_SIZE); +- b->pins[7].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; +- +- strncpy(b->pins[8].name, "P8", MRAA_PIN_NAME_SIZE); +- b->pins[8].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; +- b->pins[8].gpio.pinmap = 21; +- b->pins[8].uart.parent_id = 2; +- b->pins[8].uart.mux_total = 0; ++ b->adv_func = (mraa_adv_func_t*) calloc(1, sizeof(mraa_adv_func_t)); ++ if (b->adv_func == NULL) { ++ return NULL; ++ } + +- strncpy(b->pins[9].name, "P9", MRAA_PIN_NAME_SIZE); +- b->pins[9].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; +- b->pins[9].gpio.pinmap = 20; +- b->pins[9].uart.parent_id = 2; +- b->pins[9].uart.mux_total = 0; ++ b->adv_func->i2c_init_pre = i2c_init_pre; ++ b->adv_func->pwm_init_post = pwm_init_post; ++ b->adv_func->spi_init_pre = spi_init_pre; ++ b->adv_func->uart_init_pre = uart_init_pre; ++ b->adv_func->gpio_init_pre = gpio_init_pre; ++ b->adv_func->i2c_set_frequency_replace = &i2c_freq; + +- strncpy(b->pins[10].name, "P10", MRAA_PIN_NAME_SIZE); +- b->pins[10].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; +- b->pins[10].gpio.pinmap = 2; ++ b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * b->phy_pin_count); + +- strncpy(b->pins[11].name, "P11", MRAA_PIN_NAME_SIZE); +- b->pins[11].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; +- b->pins[11].gpio.pinmap = 3; ++ memset(b->pins, 0, sizeof(mraa_pininfo_t) * b->phy_pin_count); ++ memset(gpio_mux_groups, -1, sizeof(gpio_mux_groups)); + +- strncpy(b->pins[12].name, "P12", MRAA_PIN_NAME_SIZE); +- b->pins[12].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; +- b->pins[12].gpio.pinmap = 0; ++ b->adv_func->gpio_mmap_setup = &mraa_mtk_linkit_mmap_setup; + +- strncpy(b->pins[13].name, "P13", MRAA_PIN_NAME_SIZE); +- b->pins[13].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; +- b->pins[13].gpio.pinmap = 1; ++ for (i = 0; i < b->phy_pin_count; i++) { ++ snprintf(b->pins[i].name, MRAA_PIN_NAME_SIZE, "GPIO%d", i); ++ b->pins[i].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; ++ } + +- strncpy(b->pins[14].name, "P14", MRAA_PIN_NAME_SIZE); +- b->pins[14].capabilites = (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }; ++ strncpy(b->pins[43].name, "GPIO43", MRAA_PIN_NAME_SIZE); ++ b->pins[43].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[43].gpio.pinmap = 43; ++ gpio_mux_groups[43] = MUX_EPHY; ++ ++ strncpy(b->pins[20].name, "GPIO20", MRAA_PIN_NAME_SIZE); ++ b->pins[20].capabilites = (mraa_pincapabilities_t){ 1, 1, 1, 0, 0, 0, 0, 1 }; ++ b->pins[20].gpio.pinmap = 20; ++ b->pins[20].uart.parent_id = 2; ++ b->pins[20].uart.mux_total = 0; ++ b->pins[20].pwm.parent_id = 0; ++ b->pins[20].pwm.pinmap = 2; ++ gpio_mux_groups[20] = MUX_UART2; ++ ++ strncpy(b->pins[21].name, "GPIO21", MRAA_PIN_NAME_SIZE); ++ b->pins[21].capabilites = (mraa_pincapabilities_t){ 1, 1, 1, 0, 0, 0, 0, 1 }; ++ b->pins[21].gpio.pinmap = 21; ++ b->pins[21].uart.parent_id = 2; ++ b->pins[21].uart.mux_total = 0; ++ b->pins[21].pwm.parent_id = 0; ++ b->pins[21].pwm.pinmap = 3; ++ gpio_mux_groups[21] = MUX_UART2; ++ ++ strncpy(b->pins[2].name, "GPIO2", MRAA_PIN_NAME_SIZE); ++ b->pins[2].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[2].gpio.pinmap = 2; ++ gpio_mux_groups[2] = MUX_I2S; ++ ++ strncpy(b->pins[3].name, "GPIO3", MRAA_PIN_NAME_SIZE); ++ b->pins[3].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[3].gpio.pinmap = 3; ++ gpio_mux_groups[3] = MUX_I2S; ++ ++ strncpy(b->pins[0].name, "GPIO0", MRAA_PIN_NAME_SIZE); ++ b->pins[0].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[0].gpio.pinmap = 0; ++ gpio_mux_groups[0] = MUX_I2S; ++ ++ strncpy(b->pins[1].name, "GPIO1", MRAA_PIN_NAME_SIZE); ++ b->pins[1].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[1].gpio.pinmap = 1; ++ gpio_mux_groups[1] = MUX_I2S; ++ ++ strncpy(b->pins[37].name, "GPIO37", MRAA_PIN_NAME_SIZE); ++ b->pins[37].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[37].gpio.pinmap = 37; ++ gpio_mux_groups[37] = MUX_GPIO; ++ ++ strncpy(b->pins[44].name, "GPIO44", MRAA_PIN_NAME_SIZE); ++ b->pins[44].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[44].gpio.pinmap = 44; ++ gpio_mux_groups[44] = MUX_WLED; ++ ++ strncpy(b->pins[46].name, "GPIO46", MRAA_PIN_NAME_SIZE); ++ b->pins[46].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; ++ b->pins[46].gpio.pinmap = 46; ++ b->pins[46].uart.parent_id = 1; ++ b->pins[46].uart.mux_total = 0; ++ gpio_mux_groups[46] = MUX_UART1; ++ ++ strncpy(b->pins[45].name, "GPIO45", MRAA_PIN_NAME_SIZE); ++ b->pins[45].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; ++ b->pins[45].gpio.pinmap = 45; ++ b->pins[45].uart.parent_id = 1; ++ b->pins[45].uart.mux_total = 0; ++ gpio_mux_groups[45] = MUX_UART1; ++ ++ strncpy(b->pins[13].name, "GPIO13", MRAA_PIN_NAME_SIZE); ++ b->pins[13].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; ++ b->pins[13].gpio.pinmap = 13; ++ b->pins[13].uart.parent_id = 1; ++ b->pins[13].uart.mux_total = 0; ++ gpio_mux_groups[13] = MUX_UART0; ++ ++ strncpy(b->pins[12].name, "GPIO12", MRAA_PIN_NAME_SIZE); ++ b->pins[12].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; ++ b->pins[12].gpio.pinmap = 12; ++ b->pins[12].uart.parent_id = 0; ++ b->pins[12].uart.mux_total = 0; ++ gpio_mux_groups[12] = MUX_UART0; ++ ++ strncpy(b->pins[5].name, "GPIO5", MRAA_PIN_NAME_SIZE); ++ b->pins[5].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 1, 0, 0 }; ++ b->pins[5].gpio.pinmap = 5; ++ b->pins[5].i2c.pinmap = 0; ++ b->pins[5].i2c.mux_total = 0; ++ gpio_mux_groups[5] = MUX_I2C; ++ ++ strncpy(b->pins[4].name, "GPIO4", MRAA_PIN_NAME_SIZE); ++ b->pins[4].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 1, 0, 0 }; ++ b->pins[4].gpio.pinmap = 4; ++ b->pins[4].i2c.pinmap = 0; ++ b->pins[4].i2c.mux_total = 0; ++ gpio_mux_groups[4] = MUX_I2C; ++ ++ strncpy(b->pins[6].name, "GPIO6", MRAA_PIN_NAME_SIZE); ++ b->pins[6].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 1, 0, 0, 0 }; ++ b->pins[6].gpio.pinmap = 6; ++ b->pins[6].spi.pinmap = 0; ++ b->pins[6].spi.mux_total = 0; ++ gpio_mux_groups[6] = MUX_SPI_CS1; ++ ++ strncpy(b->pins[7].name, "GPIO7", MRAA_PIN_NAME_SIZE); ++ b->pins[7].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 1, 0, 0, 0 }; ++ b->pins[7].spi.pinmap = 0; ++ b->pins[7].spi.mux_total = 0; ++ ++ strncpy(b->pins[8].name, "GPIO8", MRAA_PIN_NAME_SIZE); ++ b->pins[8].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 1, 0, 0, 0 }; ++ b->pins[8].spi.pinmap = 0; ++ b->pins[8].spi.mux_total = 0; ++ ++ strncpy(b->pins[9].name, "GPIO9", MRAA_PIN_NAME_SIZE); ++ b->pins[9].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 1, 0, 0, 0 }; ++ b->pins[9].spi.pinmap = 0; ++ b->pins[9].spi.mux_total = 0; ++ ++ strncpy(b->pins[18].name, "GPIO18", MRAA_PIN_NAME_SIZE); ++ b->pins[18].capabilites = (mraa_pincapabilities_t){ 1, 1, 1, 0, 0, 0, 0, 0 }; ++ b->pins[18].gpio.pinmap = 18; ++ b->pins[18].pwm.parent_id = 0; ++ b->pins[18].pwm.pinmap = 0; ++ gpio_mux_groups[18] = MUX_PWM0; ++ ++ strncpy(b->pins[19].name, "GPIO19", MRAA_PIN_NAME_SIZE); ++ b->pins[19].capabilites = (mraa_pincapabilities_t){ 1, 1, 1, 0, 0, 0, 0, 0 }; ++ b->pins[19].gpio.pinmap = 19; ++ b->pins[19].pwm.parent_id = 0; ++ b->pins[19].pwm.pinmap = 1; ++ gpio_mux_groups[19] = MUX_PWM1; ++ ++ strncpy(b->pins[16].name, "GPIO16", MRAA_PIN_NAME_SIZE); ++ b->pins[16].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[16].gpio.pinmap = 16; ++ gpio_mux_groups[16] = MUX_SPI_S; ++ ++ strncpy(b->pins[17].name, "GPIO17", MRAA_PIN_NAME_SIZE); ++ b->pins[17].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[17].gpio.pinmap = 17; ++ gpio_mux_groups[17] = MUX_SPI_S; ++ ++ strncpy(b->pins[14].name, "GPIO14", MRAA_PIN_NAME_SIZE); ++ b->pins[14].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; ++ b->pins[14].gpio.pinmap = 14; ++ gpio_mux_groups[14] = MUX_SPI_S; + +- strncpy(b->pins[15].name, "P15", MRAA_PIN_NAME_SIZE); ++ strncpy(b->pins[15].name, "GPIO15", MRAA_PIN_NAME_SIZE); + b->pins[15].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; +- b->pins[15].gpio.pinmap = 44; +- +- strncpy(b->pins[16].name, "P16", MRAA_PIN_NAME_SIZE); +- b->pins[16].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; +- b->pins[16].gpio.pinmap = 46; +- b->pins[16].uart.parent_id = 1; +- b->pins[16].uart.mux_total = 0; +- +- strncpy(b->pins[17].name, "P17", MRAA_PIN_NAME_SIZE); +- b->pins[17].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; +- b->pins[17].gpio.pinmap = 45; +- b->pins[17].uart.parent_id = 1; +- b->pins[17].uart.mux_total = 0; +- +- strncpy(b->pins[18].name, "P18", MRAA_PIN_NAME_SIZE); +- b->pins[18].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; +- b->pins[18].gpio.pinmap = 13; +- b->pins[18].uart.parent_id = 1; +- b->pins[18].uart.mux_total = 0; +- +- strncpy(b->pins[19].name, "P19", MRAA_PIN_NAME_SIZE); +- b->pins[19].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }; +- b->pins[19].gpio.pinmap = 12; +- b->pins[19].uart.parent_id = 0; +- b->pins[19].uart.mux_total = 0; +- +- strncpy(b->pins[20].name, "P20", MRAA_PIN_NAME_SIZE); +- b->pins[20].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 1, 0, 0 }; +- b->pins[20].gpio.pinmap = 5; +- b->pins[20].i2c.pinmap = 0; +- b->pins[20].i2c.mux_total = 0; +- +- strncpy(b->pins[21].name, "P21", MRAA_PIN_NAME_SIZE); +- b->pins[21].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 1, 0, 0 }; +- b->pins[21].gpio.pinmap = 4; +- b->pins[21].i2c.pinmap = 0; +- b->pins[21].i2c.mux_total = 0; +- +- strncpy(b->pins[22].name, "P22", MRAA_PIN_NAME_SIZE); +- b->pins[22].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 1, 0, 0, 0 }; +- b->pins[22].gpio.pinmap = 8; +- b->pins[22].spi.pinmap = 0; +- b->pins[22].spi.mux_total = 0; +- +- strncpy(b->pins[23].name, "P23", MRAA_PIN_NAME_SIZE); +- b->pins[23].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 1, 0, 0, 0 }; +- b->pins[23].gpio.pinmap = 9; +- b->pins[23].spi.pinmap = 0; +- b->pins[23].spi.mux_total = 0; +- +- strncpy(b->pins[24].name, "P24", MRAA_PIN_NAME_SIZE); +- b->pins[24].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 1, 0, 0, 0 }; +- b->pins[24].gpio.pinmap = 7; +- b->pins[24].spi.pinmap = 0; +- b->pins[24].spi.mux_total = 0; +- +- strncpy(b->pins[25].name, "P25", MRAA_PIN_NAME_SIZE); +- b->pins[25].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 1, 0, 0, 0 }; +- b->pins[25].gpio.pinmap = 6; +- b->pins[25].spi.pinmap = 0; +- b->pins[25].spi.mux_total = 0; +- +- strncpy(b->pins[26].name, "P26", MRAA_PIN_NAME_SIZE); +- b->pins[26].capabilites = (mraa_pincapabilities_t){ 1, 1, 1, 0, 0, 0, 0, 0 }; +- b->pins[26].gpio.pinmap = 18; +- +- strncpy(b->pins[27].name, "P27", MRAA_PIN_NAME_SIZE); +- b->pins[27].capabilites = (mraa_pincapabilities_t){ 1, 1, 1, 0, 0, 0, 0, 0 }; +- b->pins[27].gpio.pinmap = 19; +- +- strncpy(b->pins[28].name, "P28", MRAA_PIN_NAME_SIZE); +- b->pins[28].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; +- b->pins[28].gpio.pinmap = 16; +- +- strncpy(b->pins[29].name, "P29", MRAA_PIN_NAME_SIZE); +- b->pins[29].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; +- b->pins[29].gpio.pinmap = 17; +- +- strncpy(b->pins[30].name, "P30", MRAA_PIN_NAME_SIZE); +- b->pins[30].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; +- b->pins[30].gpio.pinmap = 14; +- +- strncpy(b->pins[31].name, "P31", MRAA_PIN_NAME_SIZE); +- b->pins[31].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; +- b->pins[31].gpio.pinmap = 15; ++ b->pins[15].gpio.pinmap = 15; ++ gpio_mux_groups[15] = MUX_SPI_S; + + // BUS DEFINITIONS + b->i2c_bus_count = 1; + b->def_i2c_bus = 0; +- b->i2c_bus[0].bus_id = 0; +- b->i2c_bus[0].sda = 20; +- b->i2c_bus[0].scl = 21; ++ b->i2c_bus[0].bus_id = 0; ++ b->i2c_bus[0].sda = 5; ++ b->i2c_bus[0].scl = 4; + + b->spi_bus_count = 1; + b->def_spi_bus = 0; +- b->spi_bus[0].bus_id = 0; +- b->spi_bus[0].slave_s = 0; +- b->spi_bus[0].cs = 25; +- b->spi_bus[0].mosi = 22; +- b->spi_bus[0].miso = 23; +- b->spi_bus[0].sclk = 21; ++ b->spi_bus[0].bus_id = 32766; ++ b->spi_bus[0].slave_s = 1; ++ b->spi_bus[0].cs = 6; ++ b->spi_bus[0].mosi = 8; ++ b->spi_bus[0].miso = 9; ++ b->spi_bus[0].sclk = 7; + + b->uart_dev_count = 3; + b->def_uart_dev = 0; +- b->uart_dev[0].rx = 18; +- b->uart_dev[0].tx = 19; +- +- b->uart_dev[1].rx = 16; +- b->uart_dev[1].tx = 17; +- +- b->uart_dev[2].rx = 9; +- b->uart_dev[2].tx = 8; ++ b->uart_dev[0].rx = 13; ++ b->uart_dev[0].tx = 12; ++ b->uart_dev[0].device_path = "/dev/ttyS0"; ++ b->uart_dev[1].rx = 46; ++ b->uart_dev[1].tx = 45; ++ b->uart_dev[1].device_path = "/dev/ttyS1"; ++ b->uart_dev[2].rx = 21; ++ b->uart_dev[2].tx = 20; ++ b->uart_dev[2].device_path = "/dev/ttyS2"; + + b->gpio_count = 0; +- int i; + for (i = 0; i < b->phy_pin_count; i++) { + if (b->pins[i].capabilites.gpio) { + b->gpio_count++; +--- a/src/gpio/gpio.c ++++ b/src/gpio/gpio.c +@@ -113,6 +113,8 @@ + close(export); + } + ++ mraa_gpio_use_mmaped(dev, 1); ++ + init_internal_cleanup: + if (status != MRAA_SUCCESS) { + if (dev != NULL)